Because Google is such a wildly successful company and a true innovator when it comes to IT platforms, and because we know more about its infrastructure at a theoretical level than what has been built by other hyperscalers and cloud providers, it is natural enough to think that the future of computing for the rest of us will look like what Google has already created for itself.
But ironically, only by going into the public cloud business could Google have to change its infrastructure enough to actually have to make it look more like what large enterprises will need, and …
Google Fosters Another OpenStack Kubernetes Mashup was written by Timothy Prickett Morgan at The Next Platform.
Just because Intel doesn’t make a lot of noise about a product does not mean that it is not important for the company. Rather, it is a gauge of relative importance, and with such a broad and deep portfolio of chips, not everything can be cause for rolling out the red carpet.
So it is, as usual, with the Xeon E5-4600 processors, the variant of Intel’s server chips that has some of the scalability attributes of the high-end Xeon E7 family while being based on the workhorse Xeon E5 chip that is used in the vast majority of the servers …
Intel Broadwell Rollout Complete With Xeon E5 Quads was written by Timothy Prickett Morgan at The Next Platform.
We are hitting the limits of what can be crammed into DRAM in a number of application areas. As data volumes continue to mount, this limitation will be more keenly felt.
Accordingly, there has been a great deal of work recently to look to flash to create more efficient and capable system that can accelerate deeply data-intensive problems, but few things have gotten enough traction to filter their way into big news items. With that said, there are some potential breakthroughs on this front coming out of MIT where some rather impressive performance improvements have been snagged by taking a …
MIT Research Pushes Latency Limits with Distributed Flash was written by Nicole Hemsoth at The Next Platform.
Some technology trends get their start among enterprises, some from hyperscalers or HPC organizations. With flash storage, it was small businesses and hyperscalers who, for their own reasons, got the market growing, drawing in engineering talent and venture capital to give us the plethora of options available on the market today. Now, the big customers are ready to take the plunge.
It is no coincidence, then, that Pure Storage has architected systems that scale to multiple petabytes of capacity to meet their needs. Large enterprises with pressing demands for scaling in terms of both performance and capacity need a different …
A Thirst For Petabyte Scale All-Flash Arrays was written by Timothy Prickett Morgan at The Next Platform.
As we have seen with gathering force, ARM is making a solid bid for datacenters of the future. However, a key feature of many serer farms that will be looking exploit the energy efficiency benefits of 64-bit ARM is the ability to maintain performance in a virtualized environment.
Neither X86 or ARM were built with virtualization in mind, which meant an uphill battle for Intel to build hardware support for hypervisors into its chips. VMware led the charge here beginning in the late 1990s, and over time, Intel made it its business to ensure an ability to support several different …
Are ARM Virtualization Woes Overstated? was written by Nicole Hemsoth at The Next Platform.
Would you rather have tens of thousands of customers who collectively spend a lot of money but their spending rises and falls with the gross domestic product, or a couple of dozen customers who spend almost as much on your product but who do so with massive checks that are not always predictable?
For Intel, this question is moot because it has both kinds of customers, and sometimes they both take a slight pause at exactly the same time. This is precisely what happened for Intel’s Data Center Group in the second quarter of 2016, as revenue growth slowed as …
Datacenters, Poised To Spend, Take A Breather From Intel was written by Timothy Prickett Morgan at The Next Platform.
Even though the Xeon processor has become the default engine for most kinds of compute in the datacenter, it is by no means to only option that is available to large enterprises that can afford to indulge in different kinds of systems because they do not have to homogenize their systems as hyperscalers must if they are to keep their IT costs in check.
Sometimes, there are benefits to being smaller, and the ability to pick point solutions that are good for a specific job is one of them. This has been the hallmark of the high-end of computing since …
Stacking Up Oracle S7 Against Intel Xeon was written by Timothy Prickett Morgan at The Next Platform.
Big Blue does not participate in any meaningful sense in the booming market for infrastructure for the massive hyperscale and public cloud buildout that is transforming the face of the IT business. But the company is still a bellwether for computing at large enterprises, and its efforts to – once again – transform itself to address the very different needs that companies have compared to a decade or two ago are fascinating to contemplate.
In a very real way, the manner that IBM talks about its own business these days, which is very different from how it described the rising …
Systems Are The Table Stakes For IBM’s Evolution was written by Timothy Prickett Morgan at The Next Platform.
Dell recently unveiled its datacenter liquid cooling technology under the codename of Triton. Dell’s Extreme Scale Infrastructure team originally designed and developed Triton as a proof of concept for eBay, leveraging Dell’s existing rack-scale infrastructure.
In addition to liquid-cooled cold plates that directly contact the CPUs, Triton is also designed with embedded liquid to air heat exchangers to cool the airborne heat of a large number of tightly packed and hot processor nodes using 80% of the cooling capacity of the heat exchangers. That leaves 20% of Triton’s cooling capacity as “overhead”. The overhead cooling capacity is then used to …
HPC Flows Into Hyperscale With Dell Triton was written by Timothy Prickett Morgan at The Next Platform.
For the first time access to cutting-edge quantum computing is open free to the public over the web. On 3 May 2016, IBM launched their IBM Quantum Experience website, which enthusiasts and professionals alike can program on a prototype quantum processor chip within a simulation environment. Users, accepted over email by IBM, are given a straightforward ‘composer’ interface, much like a musical note chart, to run a program and test the output. In over a month more than 25,000 users have signed up.
The quantum chip itself combines five superconducting quantum bits (qubits) operating at a cool minus 273.135531 degrees …
IBM Quantum Computing Push Gathering Steam was written by Nicole Hemsoth at The Next Platform.
In the first part of this series on the proposed Cache Coherence Interconnect for Accelerators (CCIX) standard, we talked about the issues of cache coherence and the need to share memory across various kinds of compute elements in a system. In this second part, we will go deeper into the approach of providing memory coherence across CPUs and various kinds of accelerators that have their own local memory.
A local accelerator could potentially be anything. You want something to execute faster than what is possible in today’s generic processors, and so you throw specialized hardware at the problem. Still, …
Weaving Accelerators Into The Memory Complex was written by Timothy Prickett Morgan at The Next Platform.
With the increasing adoption of scale-out architectures and cloud computing, high performance interconnect (HPI) technologies have become a more critical part of IT systems. Today, HPI represents its own market segment at the upper echelons of the networking equipment market, supporting applications requiring extremely low latency and exceptionally high bandwidth.
As big data analytics, machine learning, and business optimization applications become more prevalent, HPI technologies are of increasing importance for enterprises as well. These most demanding enterprise applications, as well as high performance computing (HPC) applications, are generally addressed with scale-out clusters based on large numbers of ‘skinny’ nodes. The …
Ranking High Performance Interconnects was written by Timothy Prickett Morgan at The Next Platform.
MPI (Message Passing Interface) is the de facto standard distributed communications framework for scientific and commercial parallel distributed computing. The Intel MPI implementation is a core technology in the Intel Scalable System Framework that provides programmers a “drop-in” MPICH replacement library that can deliver the performance benefits of the Intel Omni-Path Architecture (Intel OPA ) communications fabric plus high core count Intel Xeon and Intel Xeon Phi processors.
“Drop-in” literally means that programmers can set an environmental variable to dynamically load the highly tuned and optimized Intel MPI library – no recompilation required! Of course, Intel’s MPI library supports other …
MPI and Scalable Distributed Machine Learning was written by Nicole Hemsoth at The Next Platform.
The past decade or so has seen some really phenomenal capacity growth and similarly remarkable software technology in support of distributed-memory systems. When work can be spread out across a lot of processors and/or a lot of disjointed memory, life has been good.
Pity, though, that poor application needing access to a lot of shared memory or which could use the specialized and so faster resources of local accelerators. For such, distributed memory just does not cut it and having to send work out to an IO-attached accelerator chews into much of what would otherwise be an accelerator’s advantages. With …
Drilling Into The CCIX Coherence Standard was written by Timothy Prickett Morgan at The Next Platform.
With the general availability of the “Knights Landing” Xeon Phi many core processors from Intel last month, some of the largest supercomputing labs on the planet are getting their first taste of what the future style of high performance computing could look like for the rest of us.
We are not suggesting that the Xeon Phi processor will be the only compute engine that will be deployed to run traditional simulation and modeling applications as well as data analytics, graph processing, and deep learning algorithms. But we are suggesting that this style of compute engine – it is more than …
Knights Landing Will Waterfall Down From On High was written by Timothy Prickett Morgan at The Next Platform.
Close to a year ago when more information was becoming available about the Knights Landing processor, Intel released projections for its relative performance against two-socket Haswell machines. As one might image, the performance improvements were impressive, but now that there are systems on the ground that can be optimized and benchmarked, we are finally getting a more boots-on-the-ground view into the performance bump.
As it turns out, optimization and benchmarking on the “Cori” supercomputer at NERSC are showing that those figures were right on target. In a conversation with one of the co-authors of a new report highlighting the optimization …
Optimization Tests Confirm Knights Landing Performance Projections was written by Nicole Hemsoth at The Next Platform.
Before any country can deploy an exascale system, they have to get pre-exascale prototypes into the field to test out their underlying technologies and determine what approaches have the best chance of scaling up performance and being manufactured affordably. It looks like China is looking at three different pre-exascale systems, and none of them will deploy processors or accelerators made by US companies.
It is no secret that China has wanted to develop an indigenous capability to design chips and build supercomputer-class systems, and this was true even before the US government put the kibosh on selling Intel Xeon and …
China’s Triple Play For Pre-Exascale Systems was written by Timothy Prickett Morgan at The Next Platform.
Any time a ranking of a technology is put together, that ranking is always called into question as to whether or not it is representative of reality. Rankings, such as the Top 500 list of the top supercomputers in the world, has been the subject of such debate with regards to the Linpack Fortran performance benchmark that is used to create the rankings and its relevance to the performance of actual workloads. When it comes to networking, the changes in the list in recent years are likely a better reflection of what is going on in high performance computing in …
Competition Heats Up In Cluster Interconnects was written by Timothy Prickett Morgan at The Next Platform.
As we are carefully watching here, there is a perfect storm brewing in the semiconductor space, both for manufacturers and system designers.
On the one hand, the impending demise of Moore’s Law presents a set of challenges—and opportunities—for emerging chip companies to arise and offer alternatives, often with customization cooked into the business model. And for end users, there is a rising tide of options that might lift a lot of boats if ecosystems are rapidly adopted. This is the case in the ARM space, as we’ve seen clearly this year, as well as for other architectures, including efforts from …
Startup Takes a Risk on RISC-V Custom Silicon was written by Nicole Hemsoth at The Next Platform.
As supercomputing centers look to future exascale systems, among the other pressing concerns (power consumption in particular) is adopting the right programming approach to scale applications across millions of cores.
And while this might sound like a big enough challenge on its own, it gets more complicated because it might just be that a new programming model (or system) might not be the scalability and performance answer either. It could just be that tweaking existing tools and methods can move programming evolution to programming revolution, that is, of course, if the supercomputing programmer community can agree.
Like all things in …
Supercomputing’s Scramble to Keep Thinking in Parallel was written by Nicole Hemsoth at The Next Platform.