Packet Trimming Deep Dive – Part III
Virtual Output Queue (VOQ)
The Silicon One VOQ Architecture
Instead of using dedicated deep interface buffers for packet queuing, Cisco Silicon One utilizes a Centralized Shared Memory architecture paired with a logical Virtual Output Queue (VOQ) mechanism. Because the VOQ concept is implemented within the Ingress (Rx) NPU entity, this queuing stage occurs after the initial ingress lookups but before the packet is switched across the internal fabric to the egress.
The VOQ model turns the traditional egress queuing model, where packets wait for serialization in a hardware buffer on the specific egress interface, upside down. While a VOQ is physically located on the ingress NPU, its ability to send traffic is controlled by the state of a small hardware Output Queue (OQ) on the egress interface.
Priority Mapping and Default State
As shown in Figure 9-3, a QoS policy can be created where a packet received on interface gi1/0/1 is assigned to Traffic Class 6 if the DSCP bits are set to EF (Expedited Forwarding). This configuration instantiates a VOQ specifically for that traffic class. In this hierarchy:
TC 7 (Control Plane/CS6): Mapped to OQ 1, the highest Strict Priority (Level 1).
TC 6 (DSCP-TRIMMED/EF): Mapped to OQ 2, Continue reading
Meet Our International Team