IDG Contributor Network: Zombie companies are everywhere! But there’s a cure

It’s zombie season again! Not only was The Walking Dead back with new episodes this month, but neighborhoods around the country are about to be crawling with zombies (most can be staved off with a little chocolate).In business, unfortunately, zombie season has been in full swing for some time. This is an era of digital disruption, and it’s completely changed the way business is done, but not everyone has gotten on board. Companies are persisting with outdated business models, investing in outdated products, and committed to outdated delivery methods. To me, these companies are zombies, dead without knowing it. They may be moving forward, but don’t let the motion fool you, they’re only moving toward obsolescence.To read this article in full or to leave a comment, please click here

Worth Reading: The calm before the IoT Storm (Reaper)

It’s been just over a year since the world witnessed some of the world’s top online Web sites being taken down for much of the day by “Mirai,” a zombie malware strain that enslaved “Internet of Things” (IoT) devices such as wireless routers, security cameras and digital video recorders for use in large-scale online attacks. Now, experts are sounding the alarm about the emergence of what appears to be a far more powerful strain of IoT attack malware — variously named “Reaper” and “IoTroop” — that spreads via security holes in IoT software and hardware. And there are indications that over a million organizations may be affected already. —Krebs on Security

Hybrid Fortran Pulls Legacy Codes into Acceleration Era

GPU accelerated supercomputing is not a new phenomenon with many high performance computing codes already primed to run on Nvidia hardware in particular.

However, for some legacy codes with special needs (changing models, high computational demands), particularly in areas like weather, the gap between those codes and the promise of GPU acceleration is rather large, even with higher level tools like OpenACC to bridge the divide—all without major code rewrites.

Given the limitations of porting some legacy Fortran codes to GPUs, a research team Tokyo Tech has devised what it calls, “hybrid Fortran” which is designed to “increase productivity when …

Hybrid Fortran Pulls Legacy Codes into Acceleration Era was written by Nicole Hemsoth at The Next Platform.

Applying Software Agility to Network Design

The paper we are looking at in this post is tangential to the world of network engineering, rather than being directly targeted at network engineering. The thesis of On Understanding Software Agility—A Social Complexity Point of View, is that at least some elements of software development are a wicked problem, and hence need to be managed through complexity. The paper sets the following criteria for complexity—

  • Interaction: made up of a lot of interacting systems
  • Autonomy: subsystems are largely autonomous within specified bounds
  • Emergence: global behavior is unpredictable, but can be explained in subsystem interactions
  • Lack of equilibrium: events prevent the system from reaching a state of equilibrium
  • Nonlinearity: small events cause large output changes
  • Self-organization: self-organizing response to disruptive events
  • Co-evolution: the system and its environment adapt to one another

It’s pretty clear network design and operation would fit into the 7 points made above; the control plane, transport protocols, the physical layer, hardware, and software are all subsystems of an overall system. Between these subsystems, there is clearly interaction, and each subsystem acts autonomously within bounds. The result is a set of systemic behaviors that cannot be predicted from examining the system itself. The network design process is, Continue reading

LDP retention and distribution modes

MPLS protocol uses labels to forward traffic between point A and B. These labels are binded to FECs and distributed on the network by means of different protocols like (LDP, RSVP, BGP-LS, SPRING). LDP (Label Distribution Protocol “RFC5036”) is still by far the widely used protocol among them and was developed to do label distribution …

Continue reading "LDP retention and distribution modes"

The post LDP retention and distribution modes appeared first on Cisco Network Design and Architecture | CCDE Bootcamp | orhanergun.net.

LDP retention and distribution modes

MPLS protocol uses labels to forward traffic between point A and B. These labels are binded to FECs and distributed on the network by means of different protocols like (LDP, RSVP, BGP-LS, SPRING). LDP (Label Distribution Protocol “RFC5036”) is still by far the widely used protocol among them and was developed to do label distribution …

Continue reading "LDP retention and distribution modes"

The post LDP retention and distribution modes appeared first on Cisco Network Design and Architecture | CCDE Bootcamp | orhanergun.net.

LDP retention and distribution modes

MPLS protocol uses labels to forward traffic between point A and B. These labels are binded to FECs and distributed on the network by means of different protocols like (LDP, RSVP, BGP-LS, SPRING). LDP (Label Distribution Protocol “RFC5036”) is still by far the widely used protocol among them and was developed to do label distribution […]

The post LDP retention and distribution modes appeared first on Cisco Network Design and Architecture | CCDE Bootcamp | orhanergun.net.

IPv6 generated with EUI-64 has a strange bit inside

How Does Internet Work - We know what is networking

What is universal/local bit in IPv6 EUI-64 address? One of my readers contacted me with an interesting question in comments of “IPv6 – SLAAC EUI-64 Address Format” article. The question was: “How come that the ipv6 address after the prefix is 21C:C4FF:FECF:4ED0 if the mac address is 00-1C-C4-CF-4E-D0?” Of course, we all know from the previous article that EUI-64 process is taking the interface MAC address (if that is an Ethernet interface) and it creates 64 bits Interface ID with it by shimming additional FFFE (16bits in hex) in between the MAC address bits. The reader was confused with an

IPv6 generated with EUI-64 has a strange bit inside

IDG Contributor Network: Enabling reconfigurable computing with field-programmable gate arrays

In my last column, I wrote about how the standard computing platform is being reimagined by reconfigurable computing and how hyper-scale cloud companies are leading the way with the use of SmartNICs and field-programmable gate arrays (FPGAs). Now, let’s look at why FPGAs are so powerful in this context, the major challenge of working with FPGAs, and how vendors and companies are addressing the challenge.Why FPGAs? What is it about FPGAs that makes them so different and yet so powerful compared to CPUs? One of the main reasons is that they are completely reconfigurable. Unlike ASICs, such as CPUs, the logic in the FPGA is not static but can be rearranged to support whatever workload you want to support. With an ASIC, you need to commit to a certain feature set up front, as this cannot be changed once the chip is produced. With an FPGA, you need to commit to the capabilities that the FPGA will provide with respect to available logic gates and Look-Up Tables (or LUTs), which are the tables that define how logic gates are combined to support a given function. But, what the FPGA does is entirely up to the FPGA solution developer Continue reading

IDG Contributor Network: Enabling reconfigurable computing with field-programmable gate arrays

In my last column, I wrote about how the standard computing platform is being reimagined by reconfigurable computing and how hyper-scale cloud companies are leading the way with the use of SmartNICs and field-programmable gate arrays (FPGAs). Now, let’s look at why FPGAs are so powerful in this context, the major challenge of working with FPGAs, and how vendors and companies are addressing the challenge.Why FPGAs? What is it about FPGAs that makes them so different and yet so powerful compared to CPUs? One of the main reasons is that they are completely reconfigurable. Unlike ASICs, such as CPUs, the logic in the FPGA is not static but can be rearranged to support whatever workload you want to support. With an ASIC, you need to commit to a certain feature set up front, as this cannot be changed once the chip is produced. With an FPGA, you need to commit to the capabilities that the FPGA will provide with respect to available logic gates and Look-Up Tables (or LUTs), which are the tables that define how logic gates are combined to support a given function. But, what the FPGA does is entirely up to the FPGA solution developer Continue reading

Deep Voice 3: Ten Million Queries on a Single GPU Server

Although much of the attention around deep learning for voice has focused on speech recognition, developments in artificial speech synthesis (text to speech) based on neural network approaches have been just as swift.

The goal with text-to-speech (TTS), as in other voice-related deep learning areas, is to get the training and inference times way down to allow for fast delivery of services and low power consumption and utilization of hardware resources. A recent effort at Chinese search giant, Baidu, which is at often at the forefront of deep learning for voice recognition and TTS, has shown remarkable progress on both …

Deep Voice 3: Ten Million Queries on a Single GPU Server was written by Nicole Hemsoth at The Next Platform.

1 … 1,800 1,801 1,802 1,803 1,804 … 3,795